This application is based on Japanese Patent Application 2000-221202, filed on Jul. 21, 2000 the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having a dual damascene wiring structure and its manufacture method.
In this embodiment, an xe2x80x9cetch stopperxe2x80x9d is intended to mean a layer having an etch rate of at most ⅕ times that of a layer to be etched. A xe2x80x9csimilar etch ratexe2x80x9d is intended to mean an etch rate about xc2xd to about two times that of a layer to be etched.
b) Description of the Related Art
Demands for higher integration of semiconductor devices are increasing. A conventional conductive wire is made of Al, W or the like. After an Al wiring layer or W wiring layer is formed on an insulating layer, an etching mask such as a resist pattern is formed on the wiring layer. This wiring layer is patterned and embedded in an insulating layer to form a wiring pattern.
As the integration degree becomes higher, it is required to narrow the width of a wiring pattern and shorten a space between adjacent conductive wires. Such fine patterns increase the capacitance between wiring patterns. A reduced cross sectional area of a conductive wire results in an increased resistance. An increase in the capacitance or resistance lowers a signal transmission speed in the conductive wire and hinders speeding up the device operation.
In order to reduce the wiring resistance, Cu wiring having a lower resistivity than Al and W has been adopted. Cu is difficult to be patterned by etching. A damascene wiring process is used for forming a Cu wiring pattern. Namely, a wiring trench is formed in a surface layer of an insulating film, a wiring layer is embedded in this wiring trench, and an unnecessary wiring layer on the surface of the insulating film is removed by chemical mechanical polishing (CMP).
It is necessary to interconnect wiring layers by using via conductors. A single damascene process and a dual damascene process are known as the damascene process. In the single damascene process, after a via hole is embedded with a via conductor, a wiring trench is formed and embedded with wiring material. In the dual damascene process, after a via hole and a wiring trench are formed, they are embedded with wiring material at the same time. The dual damascene process is superior in terms of process simplification.
A via first process and a trench first process are known as the dual damascene process. The former forms first a via hole and then a wiring trench, whereas the latter forms first a wiring trench and then a via hole. The via first process is considered superior in terms of reliable connection to the underlie.
With reference to FIGS. 11A to 11H, an example of the via first dual damascene process will be described.
As shown in FIG. 11A, on the surface of an underlie 110 having a conductive region 111, a first etch stopper layer 112 of SiN or the like is formed. The underlie may be a semiconductor substrate or an insulating layer formed on the substrate. The conductive region 11 may be a semiconductor region or a wiring layer. If the conductive region 111 is a Cu wire, the etch stopper layer 112 is needed to cover the Cu wire because the surface of the Cu wire is oxidized very easily.
On the first etch stopper 112, a first interlayer insulting film 113 of silicon oxide or the like is formed. On the first interlayer insulating film 113, a second etch stopper 114 of SiN or the like is formed which functions as an etch stopper while a wiring trench is formed thereon. On the second etch stopper 114, a second interlayer insulating film 115 of silicon oxide or the like is formed in which the wiring trench is formed. On the second interlayer insulating film 115, an insulating antireflection film 116 of SiN or the like is formed which presents an antireflection function while a resist layer is patterned.
As shown in FIG. 11B, a resist layer is formed on the insulating antireflection film 116, and exposed and developed to form a resist pattern PR1. The resist pattern PR1 is formed with an opening 101 corresponding to a via hole.
By using the resist pattern PR1 as an etching mask, the antireflection film 116, second interlayer insulating film 115, second etch stopper layer 114 and first interlayer insulating film 113 are anisotropically etched to form a via hole 102 in register with the opening 101 in the resist pattern PR1. If an over-etch is performed, the first etch stopper layer 112 is etched slightly. In some cases, the first etch stopper layer 112 may be completely etched and the underlying conductive region 111 may be damaged. The resist pattern PR1 is thereafter removed.
As shown in FIG. 11C, a resist layer is formed on the antireflection film 116, and exposed and developed to form a second resist pattern PR2. The resist pattern PR2 is formed with an opening 103 corresponding to a wiring trench in an area inclusive of the via hole 102.
As shown in FIG. 11D, by using the resist pattern PR2 as an etching mask, the antireflection film 116 and second interlayer insulating film 115 are etched. In this etching, the second etch stopper layer 114 functions as an etching stopper.
During this etching process shown in FIG. 11D, if the quality and thickness of the first etch stopper layer 112 are insufficient, the first etch stopper 112 may be etched and the surface of the underlying conductive region 111 may be damaged.
As shown in FIG. 11E, the second resist pattern PR2 is removed by ashing with oxygen plasma. If the first etch stopper layer 112 is not left sufficiently, oxygen plasma during this ashing process may damage the surface of the conductive region 111.
As shown in FIG. 11F, the antireflection film 116 on the second interlayer insulating film 115, the second etch stopper layer 114 exposed at the bottom of the wiring trench, and the first etch stopper layer 112 exposed in the via hole, are preferably anisotropically etched and removed. Thereafter, a damascene wiring layer 160 is formed.
During these processes, when the wiring trench is formed, the wiring trench etching is stopped at the second etch stopper layer 114. The etch stopper layer 114 is therefore left on the bottom of the wiring trench. Even if the exposed second etch stopper layer is removed, the side wall of the second etch stopper 114 layer contacts the side wall of the dual damascene wiring layer 160.
An insulating film having an etch stopper function has generally a high dielectric constant. If such an etch stopper exists at the side wall of the wiring trench, a capacitance between adjacent wiring patterns increases. In order to avoid this, a process has been proposed which does not use the second etch stopper layer when the wiring trench is etched.
As shown in FIG. 11G, after an etch stopper layer 112 and an interlayer insulating film 113 are formed on an underlie 110, an antireflection film 116 is formed on the surface of the interlayer insulating film 113. A resist pattern is formed on the antireflection film 116. Similar to the above-described processes, a via hole 102 is formed reaching the etch stopper 112. Thereafter, a resist pattern PR2 is formed for forming a wiring trench.
As shown in FIG. 11H, by using the resist pattern PR2 as a mask, the antireflection film 116 is etched and thereafter the first interlayer 113 is etched by a predetermined thickness through controlled etching. Since an etching stopper is not used, this etching depth is controlled by an etch time. In this manner, a wiring trench 104 continuous with the via hole 102 is formed. Because an etch stopper layer is not used, the shoulder of the via hole is etched so that the cross sectional area of the via hole gradually increases toward the upper area.
Also in this example, if the first etch stopper layer 112 is etched during etching of the via hole 102 and/or wiring trench 104, the surface of the underlying conductive region 111 may be damaged.
With the via first dual damascene process, there is a possibility that the etch stopper layer on the bottom of the via hole is damaged so that the underlying conductive region is damaged.
In order to make the conductive region under the via hole not susceptible to damages, a process has been proposed by which a filler is placed in a via hole.
FIGS. 12A to 12E illustrate an example of the process of placing a filler in a via hole and thereafter forming a wiring trench by utilizing an etch stopper layer.
As shown in FIG. 12A, on an underlie 110 having a conductive region 111, a laminated structure is formed having a first etch stopper layer 112, a first interlayer insulating film 113, a second etch stopper layer 114, a second interlayer insulating film 115 and an antireflection film 116. A via hole 102 reaching the first etch stopper layer 112 is formed by using a resist pattern.
A filler 155 used as an etching protective member or material is embedded in the via hole 102 at a deeper position. On the antireflection film 116, a resist pattern PR2 is formed having an opening 103 corresponding to a wiring trench.
As shown in FIG. 12B, by using the resist pattern PR2 as an etching mask, the antireflection film 116 and second interlayer insulating film 115 are anisotropically etched. In this case, the first etch stopper layer 112 on the bottom of the via hole 102 can be protected from etching because the layer 112 is covered with the filler 155.
As shown in FIG. 12C, the resist pattern PR2 is removed by ashing. If the filler 155 is made of organic substance, it can be removed at the same time by this ashing. It is also possible to remove the filler 155 and resist pattern PR2 by different processes.
The first etch stopper layer 112 is not etched by the etching process for the wiring trench. Therefore, the ashing process rarely damages the conductive region 111 under the first etch stopper layer 112.
As shown in FIG. 12D, the antireflection film 116 on the second interlayer insulating film 115, the second etch stopper layer 114 exposed on the bottom of the wiring trench, and the first etch stopper layer 112 exposed in the via hole, are etched and removed. In this manner, the wiring trench and via hole continuous with the underlying conductive region 111 are formed.
As shown in FIG. 12E, a wiring layer is deposited and this wiring layer on the surface of the second interlayer insulating film 115 is removed by CMP to form a dual damascene wiring pattern 160 embedded in the via hole and wiring trench.
As described above, unless a filler is used, a conventional dual damascene process is not always easy to sufficiently protect the surface of a conductive region disposed under a dual damascene wiring pattern and form a highly reliable wiring structure.
It is an object of the present invention to provide a method of manufacturing a semiconductor device having a highly reliable dual damascene structure capable of sufficiently protecting the surface of an underlying conductive layer.
It is another object of the present invention to provide a semiconductor device having a structure suitable for incorporating a dual damascene process.
According to one aspect of the present invention, there is provided a semiconductor device comprising: an underlie having a conductive region in a surface layer of the underlie; an insulating etch stopper film covering a surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in said interlayer insulating film, the wiring trench having a first depth from a surface of the interlayer insulating film; a contact hole extending from a bottom surface of said wiring trench to a surface of the conductive region via a remaining thickness of the interlayer insulating film and via the insulating etch stopper film; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding a side wall and the bottom surface of the wiring trench and a second kind of an insulating layer disposed under the first kind of the insulating layer and having etching characteristics different from the first kind of the insulating layer.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie; forming an interlayer insulating film on the insulating etch stopper film, the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating film, the second kind of the insulating film having etching characteristics different from the first kind of the insulating film; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film via the interlayer insulating film; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer; forming a wiring trench in the first kind of the insulating film of the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan; removing the protective filler; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes.
A manufacture method is provided for manufacturing a semiconductor device having a dual damascene wiring structure less damaging an underlying conductive region. A semiconductor device having an appropriate dual damascene wiring structure is provided. Wiring structure forming techniques are provided for forming a wiring structure rarely damaging an underlying conductive region even if a filler in a via hole is not used.